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# Meaning

## Description

$1.$Register Addressing Mode

(or)

Register Direct AM

$\text{Add} R_{1},R_{2}$ $R_{1}\leftarrow R_{1}+R_{2}$ Two General Purpose Register value is added. Operands stored in GPRs
$2.$Immediate Addressing Mode $\text{Add} R_{1},$#$4$ $R_{1}\leftarrow R_{1}+4$ Register value is added with a constant term (operands are in instruction , no need of GPRs). Here we use Instruction Register(IR)
$3.$Displacement Addressing Mode $\text{Add }R_{4},100(R_{1})$ $R_{4}\leftarrow R_{4}+M[100+R_{1}]$ Register value is added by the memory location pointed by another register with 100 as displacement(This is alternatively a Indexed Addressing Mode)
$4.$Indexed $\text{Add} R_{3},(B,I)$

$i)R_{3}\leftarrow R_{3}+M[B+I]$

$ii)\text{Add} 20(R_{1}),R_{2}$

$R_{1}\leftarrow 1000$

$iii)\text{Add} 1000(R_{1}),R_{2}$

$R_{1}\leftarrow 20$

Register value is added to memory address from base address of array  with some displacement(which work like pointer) for specific index location.It can be use a set of GPR's or called Index Registers. Also it can be done with more than one registers, called Base Registers. like$(R_{I},R_{j})$ where Second register contains offset value of X(Refer Hamacher)
$5.$Direct or Absolute $\text{Add} R_{1},(R_{2})$ $R_{1}\leftarrow R_{1}+M[R_{2}]$ Register value is added with some memory location to get effective address
$6.$Indirect AM (or) Register Indirect AM $\text{Add} R_{1},[email protected]$(R_{3})R_{1}\leftarrow R_{1}+M[M[R_{3}]]$Register value is added with memory location, which is address of memory location of the operand$7.$Base Register Addressing Add BaseReg,Off In this addressing mode Base register value added with offset value$8.$Implied Addressing$\text{Add} R_{1}, ACR_{1}\leftarrow R_{1}+AC$Accumulator value is added with register value to get effective address$9.$Relative Addressing Mode PC,offset Effective Address is calculated by adding Counter value with offset value,Here PC used as a Special Purpose Registers instead of General Purpose Registers$10.$Auto Increment Addressing$\text{Add} R_{1},(R_{2})+R_{1} \leftarrow R_{1} +M[R2]R_{2} \leftarrow R_{2} + d11.$Auto Decreasing Addressing Mode$\text{Add} R1,-(R2)R_{2} \leftarrow R_{2}-dR_{1} \leftarrow R_{1} + M[R2]\$

I have tried to collect all addressing mode and how these mode works? Is my explanation correct for every addressing mode.Is any other addressing mode exists , which am I missing? Plz check

edited | 250 views
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Is my explanation correct for every addressing mode

Yes.

Is any other addressing mode exists , which am I missing?

There are two types of direct and indirect AM..

Register direct mode  , Memory direct mode

Register indirect mode, Memory indirect mode

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is these for GATE? Can u explain
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That i don't know but there is nothing much in it.. moreover the questions usually describe the operation of AMs because the syntax varies...
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@MiniPanda

there is nothing like Memory indirect mode.

right?

I nowhere got this mode
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Base and Limit register

Base and limit registers are special hardware registers. When a process is run, the base register is loaded with the physical location where the process begins in memory. The limit register is loaded with the length of the process. In other words, they define the logical address space.

In Tanenbaum’s book, an example shows both a base and limit register loaded with 16384. He follows up with a question asking if base and limit registers will always be loaded with the same value. It is an accident that these values are the same because base and limit registers won’t always be the same. In this case where they are both the same, the program starts at location 16384 in memory and has a length of 16384 indicating that the program occupies all space between 16384 and 32768. The limit register could have easily been 4096 indicating that the program occupies all space between 16384 and 20480.

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A short summary of what I learned.(referred to hamacher also)
X(R)
here R is the register and X is any constant/offset.

for indexed addressing the register  R constains the offset and X contains the base address of the array.

X contains the offset and R contains the base  address
for both the above effective address is  X+R

for relative mode:
it is represented as X(PC).
here PC contains the address of the program counter and X represents the offset.

these are the three representations.

Apart from that there could be a representations like
(R1,R2) ->where the effective address is the contents of R1+R2.

X(R1,R2)-> the effective address is( contents of R1+R2)+X(X is the offset/constant).

R1 AND R2 are registers.

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@srestha

I think the implied mode point 8 it will be

My reason--> u give the address of R1 but the other operand the CPU considers it to be the accumulator without explicitly mentioning it.

other examples CLA (clear accumulator.),CMA,RLC.

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yes..
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