0 votes 0 votes Its a snapshot from hamacher. According to me there should be stall of 2 cycles why 3 ?? Because after Write stage the data will be available in register file so why extra stall in 6th clock cycle ? CO and Architecture pipelining co-and-architecture stall + – Na462 asked Sep 3, 2018 Na462 907 views answer comment Share Follow See all 13 Comments See all 13 13 Comments reply Show 10 previous comments Na462 commented Oct 5, 2018 reply Follow Share Brother in book page 477 last line it too says it stalls for 2 cycles. 0 votes 0 votes Swapnil Naik commented Oct 5, 2018 reply Follow Share @Na462 in book they are using 4 stage pipeline, in above question we have 5 stage pipeline. 0 votes 0 votes reboot commented Dec 12, 2020 reply Follow Share They have considered that there is no overlapping between WB and ID phase. And therefore ID phase has to wait until the values have been written back. (no forwarding obviously) 0 votes 0 votes Please log in or register to add a comment.
0 votes 0 votes according to me- when value of r2 register write back by instruction first then it will be decoded and fetched by second instruction so if you put decode stage at sixth cycle your [problem will be solved sachin486 answered Jul 21, 2020 sachin486 comment Share Follow See all 0 reply Please log in or register to add a comment.
