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https://gateoverflow.in/1388/gate2005-65

$\text{In this question, what will be the number of }$ $\textbf{cycles}$ $\text{needed during execution cycle of instruction}$

$\text{According to me I am getting 6 cycles. Please tell what could be the correct answer for it}$

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A and B are memory addresses

let's divide them @B is nothing but contents are specified within an address which is present in some other address.

for eg let's say B be 1002H then first we need to visit 1002H, the content will be another memory address let it be 7000H, now visit 7000H - let content be 20H.

You have to access memory twice in this case.

you know the content of R0, no need of memory access(It doesn't have to access main memory), so content in R0 will act as offset to address A hence we need to first calculate A+[R0] now we will get effective address, we need to fetch the content of this memory location from main memory which will take 1 memory clock cycle, and in the end we are going to store result in A+[R0] for which we need 1 clock cycles. so total 4 clock cycles.

This was the comment of Bikram sir, hope it may help

Instruction Cycle --> Instruction Fetch State 1 Mem Ref

Execution Cycle--> Instruction Decode State 2 Mem Ref (as in the instruction fetch state  ,we come to know that it is 3 Word Instruction, so remaining 2 Mem Ref)

------------ This 2 are part of Fetch+Decode phase and NOT execution phase !! -----------

Execution Cycle--> Operand Fetch State-> Source1 1st Mem Ref and  get address of 2nd operand 2nd mem ref  [ total 2 memory reference ]

Execution Cycle--> get the operand from given mem address-> 1Mem Ref. [ total 1 memory reference ]

Execution Cycle--> Write Back State-> 1 Mem Ref.  [ total 1 memory reference ]

so total 4 memory reference { 2 + 1 + 1 = 4 } in execution phase only .

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