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According to me "In busrt mode Already Control signal has been passed to DMA to perform action. Move data from source todestination with total no of bytes to be transfered . Then it strts performing action and on completion sends a signal to processor that task has been  ocmpleted annd left command over data and address bus. In this whole phenamenon control bus required at initalisation of task and after completion" . So in burst mode only data and address buses  are required.

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