0 votes 0 votes Assume the initial state of the clock and the flip flop is LOW (=0). If the frequency of the clock signal is f with 50% duty cycle and the flip-flop delay (< Tclk/2) the output frequency is ? Digital Logic digital-logic flip-flop testbook-test-series + – Prakhar Yadav 1 asked Sep 13, 2018 • edited Mar 12, 2019 by ajaysoni1924 Prakhar Yadav 1 426 views answer comment Share Follow See all 0 reply Please log in or register to add a comment.