Hit miss

Little confusion with these questions.What will be o/p for these two questions one with Write back and the other is Write through.1.)A 128 word cache and main memory are ...

Hemanth_13

808 views

Hemanth_13 asked Nov 7, 2018

CO and Architecture
co-and-architecture
cache-memory
write-through
write-back
effective-memory-access
numerical-answers

+ –

2 votes

0 answers

Shubhanshu asked Sep 27, 2017

1,065 views

Calculate the hit time
Assume that a hypothetical system in which program execution gives 200 stall cycles per instruction on an average. There are 260 and 120 misses in L1 (Level1) and L2 (Level2) cache out of total 1000 CPU references. If L2 to memory miss penalty is twice the hit time. ... cycles)? [Given 2.5 memory reference per instruction] a. 300, 600 b. 400, 800 c. 160, 320 d. 160, 340

Assume that a hypothetical system in which program execution gives 200 stall cycles per instruction on an average. There are 260 and 120 misses in L1 (Level1) and L2 (Lev...

Shubhanshu

1.1k views

Shubhanshu asked Sep 27, 2017

CO and Architecture
co-and-architecture
cache-memory
effective-memory-access

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0 votes

0 answers

eyeamgj asked Sep 15, 2018

173 views

self doubt write back cache
https://gateoverflow.in/35154/write-back-and-write-through every thing is clear but a doubt is tht why only the case of dirty bit is considered ...and why the case of clean bit is left while solving ??? and when to take both cases??should be explicitly mentioned in the question??

https://gateoverflow.in/35154/write-back-and-write-through every thing is clear but a doubt is tht why only the case of dirty bit is considered ...and why the case of cle...

eyeamgj

173 views

eyeamgj asked Sep 15, 2018

CO and Architecture
co-and-architecture
cache-memory
write-back
self-doubt

+ –

0 votes

0 answers

Balaji Jegan asked Sep 10, 2018

277 views

CACHE SELF DOUBT 1

Balaji Jegan

277 views

Balaji Jegan asked Sep 10, 2018

CO and Architecture
co-and-architecture
cache-memory
numerical-answers
write-back
self-doubt

+ –

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