#CO pipeline doubt

Question

Consider a 4 stage pipeline processor. The number of cycles needed by the four instructions I1, I2, I3, I4 in stages S1, S2, S3, S4 is shown below:

 

 

What is the number of cycles needed to execute the following loop?

For (i=1 to 2){I1; I2; I3; I4;}

A) 16

B) 23

C) 28

D) 30

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The answer given is- 23

My doubt is- why in 6th cycle we are introducing I4 {S1} while I3 {S2} hasn't gone to next stage?

In this question if we take the above approach, we will get different answer, according to me, I4 {S1} will be introduced in 7th clock.

because- In pipeline execution, each stage produces output to a buffer and next stage takes it from there. So, unless the previous instruction(here I3) goes to the next stage, the current instruction(I4) cannot execute a given stage

P.S.- Refer here- https://gateoverflow.in/244642/%23co-gate-2009-self-doubt

Comments

That is highly unlikely to happen and even if it does then they might ask minimum clock cycles needed.

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Thanks Swapnil!

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@Swapnil Naik

what does multiple buffer concept means in pipeline?