Branch Offset

Question

 

Consider a processor where each instruction size is exactly two bytes long. Conditional and unconditional branch instructions use PC relative addressing mode with offset specified in Bytes to the target location of the branch instruction; the offset is always with respect to the address of the next instruction in the program sequence. The below program is executed (All values are specified in decimal), type of memory is byte addressable 
 

 

Comments

let the starting address be 100

k        100-101

k+1     102-103

k+2     104-105  //branch instruction so pc =106

k+3       106-107

k+4       108-109

k+5        110-111

k+6         112            //target address

ta=pc+offset

offset=112-106=+6

Answer 1

Instruction size is 2 byte long.

Lets assume 100 as starting Address.

Instruction No	Instruction	Counting
K		100-101
K+1		102-103
K+2		104-105, Here Branch takes place, So PC = 106
K+3		106-107
K+4		108-109
K+5		110-111
k+6		112          mentioned that K+6 is  Target Address

PC relative Mode is used  TA = PC+ offset

                                          112 = 106 +Offset 

                                          offset = 6.