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If you observe the nature of pipeline you can avoid this drawing(given in answer by swapnil) in the following way.
For single-stage buffer case-I1 instruction is finishing (Latency of I1)in 7 cycles + now throughput of the pipeline is 2 cycles(we can not avoid stall here and hence need to include a worst-case delay for each stage) so next remaining three instructions will be finishing in 2*3=6 cycles. So in this way, all instruction will be finishing in 7+6=13 clock cycles.

Note-You can extend this concept for 2 times as asked in question which will be 7+2*7=21 cycles

Multi-stage buffer case- Here you have to look for specific conditions where is stall in the pipeline and whether you can avoid a stall and hence is the reduction of a number of cycle possible??
Look in table instruction I2 in S2 stage is taking 2 cycles and the following instruction I3 is taking one cycle in S1 stage and hence stall is bound to happen (Because S1 will finish its job early but S2 is not free to go forward) and hence I4 can not come in S1 stage(generally the fetch stage in processor). Here we can avoid one cycle stall and hence 20 cycles.

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