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Certainly, the DM cache will require only single Cache Index decoder, whereas the Fully - Associative Cache will not require any.

My question is - How many Index decoders do we need for K-way set associative cache? Is it just one or K ?

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The whole thing is the first the set no. Is selected by the address as the address is divided into 3 parts 1st tag bits,2nd set no, and last block offset so we first need to select the set no in which the folling address is mapped to so we need a decorder to select that set no then ....so it depends on no. Of sets....irrespective of k way associative and also we need a k comparator and size is tag bit comparator

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