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+13 votes
State True or False with one line explanation

Expanding opcode instruction formats are commonly employed in RISC. (Reduced Instruction Set Computers) machines.
asked in CO & Architecture by Veteran (59.9k points)
retagged by | 1.2k views

2 Answers

+21 votes
Best answer

I think the answer is TRUE.

RISC systems use fixed length instruction to simplify pipeline.

eg: MIPS, PowerPC: Instructions are $4$ bytes long.

CISC systems use Variable-length instructions.

eg: Intel $80X86$: Instructions vary from $1$ to $17$ bytes long.

Now the challenge is: How to fit multiple sets of instruction types into same (limited) number of bits (Fixed size instruction)?

Here comes Expanding opcode into the picture. 

RISC systems commonly uses Expanding opcode technique to have fixed size instructions. 

answered by Boss (17.4k points)
edited by
@bikram sir Please tell a good source to read Expanding Opcodes and their numericals?

this is true for more conformation look in below given link.

from 25 minute. 

+5 votes

This expanding opcode scheme makes the decoding more complex. Instead of simply looking at a bit pattern and deciding which instruction it is, we need to decode the instruction something like this: 

if (leftmost four bits != 1111 ) {
 Execute appropriate three-address instruction}
else if (leftmost seven bits != 1111 111 ) {
 Execute appropriate two-address instruction}
else if (leftmost twelve bits != 1111 1111 1111 ) {
 Execute appropriate one-address instruction }
else {
 Execute appropriate zero-address instruction

At each stage, one spare code is used to indicate that we should now look at more bits. This is another example of the types of trade-offs hardware designers continually face: Here, we trade opcode space for operand space. 


Being more complex and RISC not needing more instructions expanding opcode is not a common RISC technique. But this is there in many RISC machines. 

answered by Veteran (400k points)
@arjun sir and @bikram sir

choose best answer right one.

hem chandra joshi  

Best answer is chosen already , it is true not always false .

Many RISC machines use expanding opcode technique.

see what question says " Expanding opcode instruction formats are commonly employed in RISC."

this is true , even Arjun said that in last line .

link not working

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