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Best answer
47 votes
47 votes

I think the answer is TRUE.

RISC systems use fixed length instruction to simplify pipeline.

eg: MIPS, PowerPC: Instructions are $4$ bytes long.

CISC systems use Variable-length instructions.

eg: Intel $80X86$: Instructions vary from $1$ to $17$ bytes long.

Now the challenge is: How to fit multiple sets of instruction types into same (limited) number of bits (Fixed size instruction)?

Here comes Expanding opcode into the picture. 

RISC systems commonly uses Expanding opcode technique to have fixed size instructions. 

edited by
9 votes
9 votes

This expanding opcode scheme makes the decoding more complex. Instead of simply looking at a bit pattern and deciding which instruction it is, we need to decode the instruction something like this: 

if (leftmost four bits != 1111 ) {
 Execute appropriate three-address instruction}
else if (leftmost seven bits != 1111 111 ) {
 Execute appropriate two-address instruction}
else if (leftmost twelve bits != 1111 1111 1111 ) {
 Execute appropriate one-address instruction }
else {
 Execute appropriate zero-address instruction
} 

At each stage, one spare code is used to indicate that we should now look at more bits. This is another example of the types of trade-offs hardware designers continually face: Here, we trade opcode space for operand space. 

Ref: http://www.fatih.edu.tr/~emanetn/courses/spring2006/ceng252/ceng252_lecture3.pdf or archive

Being more complex and RISC not needing more instructions expanding opcode is not a common RISC technique. But this is there in many RISC machines. 

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