The Gateway to Computer Science Excellence
0 votes
66 views

 

closed as a duplicate of: Digital Logic: Gate2016 ECE
in Digital Logic by Loyal (6.8k points)
closed by | 66 views
+1
My answer is : 7 please verify

Approach:-

At first level the delay of nor and not gate = 2

At second level delay of MUX = 1.5

At third level delay of nor and not gate = 2

At last level delay of MUX = 1.5

SO total delay = 7
0
yes I also got the same
0
total delay : 6
0
9 nsec
0
in this case two answeris possible first one is  5 ns if  t=0

and  6 if T=1
0
@Magma why 6?
0
how?
0
it T =1 then in this cae 6nsec
0
can u derive?
0
if T=0 then first input select in first mux and second i/p selected in the case of second mux. and T=1  VICE versa

Related questions

Quick search syntax
tags tag:apple
author user:martin
title title:apple
content content:apple
exclude -tag:apple
force match +apple
views views:100
score score:10
answers answers:2
is accepted isaccepted:true
is closed isclosed:true
50,666 questions
56,168 answers
193,841 comments
94,045 users