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Delay in the circuit
[closed]
Na462
asked
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Digital Logic
Sep 29, 2018
closed
Sep 29, 2018
by
Shaik Masthan
733
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closed as a duplicate of:
Digital Logic: Gate2016 ECE
digital-logic
digital-circuits
Na462
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Digital Logic
Sep 29, 2018
closed
Sep 29, 2018
by
Shaik Masthan
by
Na462
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Chandrabhan Vishwa 1
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Oct 2, 2018
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it T =1 then in this cae 6nsec
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srestha
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Oct 2, 2018
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can u derive?
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Chandrabhan Vishwa 1
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if T=0 then first input select in first mux and second i/p selected in the case of second mux. and T=1 VICE versa
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