0 votes 0 votes closed as a duplicate of: Digital Logic: Gate2016 ECE Digital Logic digital-logic digital-circuits + – Na462 asked Sep 29, 2018 closed Sep 29, 2018 by Shaik Masthan Na462 740 views comment Share Follow See all 10 Comments See all 10 10 Comments reply Na462 commented Sep 29, 2018 reply Follow Share My answer is : 7 please verify Approach:- At first level the delay of nor and not gate = 2 At second level delay of MUX = 1.5 At third level delay of nor and not gate = 2 At last level delay of MUX = 1.5 SO total delay = 7 1 votes 1 votes srestha commented Sep 29, 2018 reply Follow Share yes I also got the same 0 votes 0 votes Magma commented Sep 29, 2018 reply Follow Share total delay : 6 0 votes 0 votes Raghav Khajuria commented Sep 29, 2018 i moved by Shaik Masthan Sep 29, 2018 reply Follow Share 9 nsec 0 votes 0 votes Chandrabhan Vishwa 1 commented Oct 2, 2018 reply Follow Share in this case two answeris possible first one is 5 ns if t=0 and 6 if T=1 0 votes 0 votes srestha commented Oct 2, 2018 reply Follow Share @Magma why 6? 0 votes 0 votes Chandrabhan Vishwa 1 commented Oct 2, 2018 reply Follow Share how? 0 votes 0 votes Chandrabhan Vishwa 1 commented Oct 2, 2018 reply Follow Share it T =1 then in this cae 6nsec 0 votes 0 votes srestha commented Oct 2, 2018 reply Follow Share can u derive? 0 votes 0 votes Chandrabhan Vishwa 1 commented Oct 2, 2018 reply Follow Share if T=0 then first input select in first mux and second i/p selected in the case of second mux. and T=1 VICE versa 0 votes 0 votes Please log in or register to add a comment.