Pipeline performance reduced if different stages have different execution delays

Question

The pipeline performance is reduced if the different stages of a pipeline have different delays

I know that in the pipeline, Tclock is taken as the Max(Ti)+Tbuffer time, and so, if the pipeline stages have different delays, then Tclock will be equal to the max delay of some stage plus the max delay of the buffer.

But, I am really not able to visualize this fact that having different delays for the different stages of the pipeline will affect the performance. Please explain ?

Comments

if 5 stages are there in pipeline IF,ID,EX,MA,WB lets takes time 1,2,3,4,5 respectively

so for execution of single instruction in non-pipeline will take (1+2+3+4+5) =15 sec .

but in case of pipeline it will take 5*max{1,2,3,4,5} = 25 sec.