zeal test digital logic

Question

i marked the option b) but i didn't understand the solution

Answer 1

Basics about NAND gate:-

If atleast one input is 0, then output is 1

If all inputs are 1, then output is 0

By knowing one input of it equal to 1, we can't decide output is either 0 or 1.

 

case 1:-  S' = 0 ===> Q = 1 and R' = 0 ====> Q' = 1, at a time Q and Q' is 1, therefore it is invalid combination.

case 2:-  S' = 0 ===> Q = 1, this is fed back into 2^nd i/p of NAND₂ gate and R' = 1 ====> it produce 0 ==> Q'=0

case 3:-  S' = 1 ===> can't decide about Q and R' = 0 ==> Q' = 1, this is fed back into 2^nd i/p of NAND₁ gate ==> it produce 0 ==> Q=0

case 4:-  S' = 1 ===> can't decide about Q and R' = 1 ====> can't decide about Q' , then assume previous value of Q

       i) previously Q=0 ====> new values are Q=0 and Q'=1

       ii) previously Q=1 ====> new values are Q=1 and Q'=0

   ∴ if S'=1 and R'=1, output is Previous Value.

for clarity image https://drive.google.com/open?id=1TyoERd7i0efFyf7nwMqTBAiC60LfUTuk

Comments

@shaikh Ur solution is perfect

Pease let me know that the solution provided by them is correct or not ?

---

it is also correct, but in the explanation they provided from t=2 to t=9 only.

without marking times in wave form, it is somewhat difficult to understand, thatswhy i provided full information.