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19 votes
  1. Assume that a CPU has only two registers $R_1$ and $R_2$ and that only the following instruction is available $XOR \: R_i, R_j;\{R_j \leftarrow R_i \oplus R_j, \text{ for } i, j =1, 2\}$

    Using this XOR instruction, find an instruction sequence in order to exchange the contents of the registers $R_1$ and $R_2$

  2. The line p of the circuit shown in figure has stuck at 1 fault. Determine an input test to detect the fault.


in CO and Architecture
edited by
Circuit Diagram Given in Gate overflow Book is wrong, Sir Please correct it.

3 Answers

19 votes
Best answer

$R$1 $\leftarrow$ R1 XOR $R2$

$R2$ $\leftarrow$ R2 XOR $R1$

$R1$ $\leftarrow$ R1 XOR $R2$

Stuck at $0$ fault :: A stuck-at fault is a particular fault model used by fault simulators and automatic test pattern generation (ATPG) tools to mimic a manufacturing defect within an integrated circuit. Individual signals and pins are assumed to be stuck at Logical '1', '0' and 'X'.

Stuck at line $1$ means no matter whatever input we provide to the line the output is always $1.$
Now, when we take $A=1 ,B=1,C=1$ the required output ,if no fault is there should be $1.$

But, since line p is stuck at logic $1$ final output of A NAND B will be $1$ only .So, final circuit output becomes $0.($which is wrong$)$


edited by
given gates are and or nand ?
I think Nand :P
for Part (a)

R2<- R1 XOR R2

R1<- R2 XOR R1

R2<- R1 XOR R2

this is correct or not?

@Vidhi &@shikha 


A=1 , B=1 C=1

the required output ,if no fault is there should be 0 and not 1.

(   (  (A=1).(B=1)  )    .  (C=1)    )'

(    (          1          )    .   (  1   )   )'

( 1)' =0

Here is how I solved this question

NAND table

1 NAND 0 -> 1  

0 NAND 0 -> 1

1 NAND 1 -> 0

If we provide 0 to C. And even if output of AND gate is 0 or 1 (stuck at 1) , output of NAND gate will still be 1.

Hence no use of providing 0 to C. Hence we provide 1 to C.

Now if output of AND is 1 then output of NAND will be 0

 &    if output of AND is 0  then output of NAND will be 1

       But if output of AND is stuck at 1 then output of NAND will be never be 1

Hence to test this we intentionally make output of AND 0, either by (A=0 & B=0) or (A=1 & B=0) or (A=0 & B=1)

What does this symbol represents??


It means there is fault either 0 ,1 or X.

I dont think the answer to the second part is correct.


Theres is one AND gate and one NAND gate.



using 1, 1, 1 will not give the correct results.


But instead 0 0  1 or 0 1 1 or 1 0 1 should give the correct results.
10 votes
R2 $\impliedby$ R1 $\oplus$ R2
R1 $\impliedby$ R2 $\oplus$ R1
R2 $\impliedby$ R1 $\oplus$ R2

(b) A=1, B=1, C=1 should give output as 1 but as p is struck at 1 fault the output comes out to be 0.
What is stuck at 1 fault???

Rajarshi Sarkar At

R2 âŸ¸ R1 âŠ• R2
R1 âŸ¸ R2 âŠ• R1
R2 âŸ¸ R1 âŠ• R2

Why R2 is written two times?


@Utkarsh Anand

How to swap two number using XOR? You can check here, a very beautiful explanation is given.

We can swap two variables (a,b) in c language as:




Now here a and b will be having one bit only. So one bit addition of two numbers can be done by half adder.

Sum=diff=a exor b

a=a exor  b

b=a exor  b

a=b exor  a

thanks @ for providing good reference to understand concept more clearly.

5 votes
stuck at 1 fault means we have doubt that p is always giving one , so we should give input (test vector ) such a way that it will pass input through the p as we have given for that input of A*B=0 for that three vectors (a=0,b=0),(a=1,b=0),(a=0,b=1) , now, how we will make sure that p is passing right input given by us or not when we put C=1 , and final output =0 it means yess , p has not stucked at 1


so test vector will be (a=0,b=0,c=1)(a=0,b=1,c=1)(a=1,b=0,c=1) so three test vectors are there for this question
you are assuming and gate ?

i think they are nand

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