0 votes 0 votes Approach : CO and Architecture co-and-architecture pipelining gatebook + – HeadShot asked Oct 7, 2018 • retagged Aug 14, 2022 by Shubham Sharma 2 HeadShot 392 views answer comment Share Follow See all 7 Comments See all 7 7 Comments reply Show 4 previous comments HeadShot commented Oct 7, 2018 reply Follow Share @MiNiPanda Conceptually if we see then i think, in case of sequential execution there is no need of buffers then are we taking it just for sake of answer matching ? Plz correct if my concept going wrong somewhere. 0 votes 0 votes HeadShot commented Oct 7, 2018 reply Follow Share @MiNiPanda I tried it by taking random values ( i consider same clock time) , may be i should have tried using different clock rate but will it be a correct approach , solving by values ? Plz have a look. 0 votes 0 votes MiNiPanda commented Oct 7, 2018 reply Follow Share Yes in sequential execution we don't need buffers. I just showed for pipelining not for non-pipelining system. I got D) for next question Let no. of instructions in the entire code be n. And time taken be t secs. Also i consider each instruction takes same time so here 1 inst will take n/t secs. n/2 insts. will take t/2 secs. The speed up is done on these n/2 instructions i.e. in the current scenario the time taken for n/2 instructions be x secs. Then speedup=(time taken before on n/2 insts)/(time taken now on n/2 insts) => 50= (t/2)/x => x= t/100 For rest of the n/2 insts. in current model will take t/2 secs as no improvement is done on that. So total time taken is t/100+t/2=51t/100 Over all speed up= (total time before)/(total time now) =t/(51t/100) =1.96 So atmost 2 1 votes 1 votes Please log in or register to add a comment.