combinational circuit

Question

x and y are two n-bit numbers. These numbers are added by a n-bit carry lookahead adder, which uses k logic levels. If the average gate delay of carry lookahead adder is d then what will be the maximum delay of carry lookahead adder circuit?

a) n$^{2}$

b) kd

c) nkd

d) nd

explain briefly..

Comments

shouldn't it be kd. as there are k-levels and delay of each level is the delay of the longest delay gate of each level, which is given here as d. hence kd.

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Yes correct

Answer 1

C4 = G3 + P3G2 + P3P2G1 + P3P2P1Go +P3P2P1PoCo

Gi=XiYi , Pi=Xi+Yi

Ci+1 = Gi + Pi(Ci)

At level1:  G3 =X3Y3, P3=X3+Y3, G2 =X2Y2, P2 =X2+Y2 ,G1 =X1Y1, P1 =x1+Y1,G0 =XoYo,Po=Xo+Y0  (AND OR GATES is used)

At level2:  P3G2 , P3P2G1 , P3P2P1Go ,P3P2P1PoCo (AND GATES is used)

At level3: C1 C2 C3 C4

At level 4: Sum you will get.

Average Gate delay is d and K level mentioned  Kd.