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When Clear input is low (since active low  signal) , the output of the flipflop is reset to 0, independent of clock pulse.

Look at the diagram LSB == Q0 AND MSB = Q3 

When the NAND gate output is zero then flipflop is reset independent of clock pulse.

But NAND gate output is Zero only when both inputs are 1.

Inputs of NAND gate are connected to Q3 and Q2 ==> Q3=1,Q2=1,Q1=0,Q0=0 

MOD-12 counter states are 0,1,2,3,4,5,6,7,8,9,10,11.

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See the key fact behind such question on finding mod value of n bit asynchronous ripple counter which can be less than 2n is you have to examine when there is a glitch and the counter again begins counting from 0.

So, what we do is since we have 4 bit ripple counter here , what we do is we assign '1' to those bits which are given to NAND gate [because those bits are responsible for resetting the counter to count from 1 as we know 1 NAND 1(in case 2 inputs to NAND gate or 1 NAND I NAND 1(in case of 3 inputs to NAND gate) as the case may be]. And the remaining bits are assigned '0'.

So here Q3 and Q2 are connected to the NAND gate and hence we set them to 1 and assign Q1 and Qto 0.Hence ,

Q3Q2Q1Q0  value = 1100

Hence mod value is nothing but decimal value of Q3Q2Q1Q0 which is decimal value of 1100 = 12

Hence mod value of the above ripple counter = 12

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ans should be mod-11 counter cause when the 1st unused state (here it is 12) comes the circuit goes back to initial state.
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