closed by
633 views
0 votes
0 votes

Q:-min  number of NAND gate required to realize Full Adder  circuit? (NAND   gate is 2 input NAND gate)

A-7

B-8
C--9
D-10

closed by

Related questions

0 votes
0 votes
2 answers
1
shgarg asked Nov 12, 2018
1,638 views
x and y are two n bit numbers. these numbers are added by n bit carry look ahead adder which uses k logic levels. if the average gate delay of carry look ahead adder is d...
1 votes
1 votes
2 answers
2
0 votes
0 votes
3 answers
3
shivangi5 asked Dec 4, 2017
1,310 views
A 1-bit full adder circuit takes 5 ns to generate the carry-out bit and 10 ns for the sum-bit. When 4, 1-bit full adders are cascaded, the maximum rate of additions per s...