ME Test series

Question

Suppose a switch is built using a computer workstation and that it can forward packets at a rate of 500,000 packets per second, regardless (within limits) of size. Assume the workstation uses direct memory access (DMA) to move data in and out of its main memory, which has a bandwidth of 2 Gbps, and that the I/O bus has a bandwidth of 1 Gbps. At what packet size would the bus bandwidth become the limiting factor?

Comments

5kb?

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Just a quick question, Switches aren't there in syllabus right?

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let x be the packet size then

5 * 10^5 * x <= 10^9 

x = 2000 bits = 250Bytes

 

But in ME test series solution it is given as 125B as they have taken IO BUS SPEED AS 1/2 of IO don't understand why? Please explain someone.