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How to do these questions? there is no information about no. of stages an instruction takes?

 

Consider the 2 GHz clock frequency processor used execute the following program segment.

Assume the 3 clock cycles required for Register to/from memory transfer, 1 clock cycle for ADD with both operands in register, 2 clock cycle MUL with both operands in register, 3 clock cycles per word for instruction fetch and decode. What is the total time required to complete the program execution (in ns)?

 

A) 12

B) 15

C) 18

D) 25

 

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It is not a question of pipeline. you can say that it is based on machine instruction.

there are 6 instruction with 8 words so fetching and decoding of instruction will take 8x3 = 24 cycles (3 cycle per word)

3 move instruction so 3x3 = 9 cycles for memory transfer and at last 2 cycles for multiply and 1 -1 cycle for addition and halt.

so number of total cycle will be 36 cycle multiplying it with 1/frequency you will get 18ns as answer

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