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2 Answers

1 votes
1 votes

As per question we have arrangement as shown in fig .

We have arranged the registers are  Q0,Q1,Q2,Q3 input to Q0 is  ((Q2 ex-or Q3) Ex-Or Q0)

as per current values we have Q0,Q1,Q2,Q3 as 1000 now ,

                 

CLOCK NUMBER Q0 Q1 Q2 Q3 INPUT At D (Q2 exor Q3 exor Q0)
 its already loaded input 1 0 0 0

1

CLOCK 1  0 0 1
CLOCK 2  1 1 0 0
CLOCK 3  0 1 1 1 0
CLOCK 4 0 0 1 1 0
CLOCK 5  0 0 0 1 1
CLOCK 6 1 0 0 0 DESIRED OUTPUT GOT.

Hence in 6th clock we got output as 1000

0 votes
0 votes
This will be the sequence after each clock cycle:

0001(in order Q0, Q1, Q2, Q3)

1000

1100

1110

0111

0011

0001

1000

After 7th clock cycle, we will get 1000.

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