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Assume a demand paged memory management system with the following characteristics:

page size = 2^12 bytes

physical address space = 2^24 bytes

logical address space = 2^32 bytes

TLB size = 2^6 bytes

How many page table entries can fit in the TLB if each entry only contains the information needed for logical to physical translation?

A) 16

B)32

C) 22

D)24

3 Answers

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page size = 2^12

LAS = 2^32

PAS = 2^24

no of pages =LAS/page size = 2^ 20 , so 20 bits required to adreess a page

frame = PAS/page size = 2^24/2^12 = 2^12 , so 12 bits needed to adreess frame

page table entry will contain page and frame  so total bits in PTE = 12+20 = 32 bits

TLB size = 2^6 . so total no of PTE that can fit in it = 2^6/(32/8)    {as 32 is in bits so divide by 8 to convert to bytes }

= 16
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yeah i too got confused but after studying about TLB i got cleared.

TLB stores the recently or frequently accessed frame number(adress-base+number).

TLB check whether it is hit or miss we need tag bits

TLB entry =tag bits + frame no bits

here tag bits is page no bits

therefore TLB entry = page no bits + frame no bits

pagenumber =32(PSE)-12(offset)=20

frame number=24-12=12

tlb entry contains 32bits=4bytes

there fore no of enteries in TLB is 2^6/4=16
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LA = 232

PA =224  Page Size = 212

Number of pages = 232 / 212 = 20 bits willbe used to address pages

Number of frame =  224 / 212 =12 bits will be used to address number of frames

Since TLB is used so its Page Table Entry = page no + Frame no

                                                                         = 20+12 = 32 bits = 4 Bytes

Page Table size = No of entries * Page Table Entry size

2Bytes = No of entries * 4 B

No of Entries = 16

 

                     

 

 

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