in Digital Logic
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in Digital Logic
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All the flipflops will operate at the same time. N-1th flipflops previous state o/p will be the input as current input to  nth. So there won't be any delay. All will run in parallel
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I have just one doubt , say I have 3 FF ,Now output of 1st flip flop is connected to input of 2nd FF and output of 2nd FF is connected to input of 3rd FF .

Now until we get op of 2nd FF , how can we get OP of 3rd FF , so we should take into consideration the delay of all flip flops .
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1 Answer

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Its synchronous counter so ,

Propagation delap = T(f-f)+ T(combinational)

T(pdsyn) = 15 + 5 =20 ns

F= 1/T(pdsyn) = 50 HZ

1 comment

So answer will be option A as we require min clock of 20ns . but clock time more than 20ns is allow but less is not allowed
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