1 votes 1 votes radha gogia asked Nov 1, 2018 radha gogia 2.8k views answer comment Share Follow See all 6 Comments See all 6 6 Comments reply Magma commented Nov 1, 2018 reply Follow Share T CLK >= T propagation_delay Propagation delay = T FF + T combinational TCLK >= 15 + 5 = 20 ns Frequency CLK = 1/20 = 50 Mhz 0 votes 0 votes Hemanth_13 commented Nov 1, 2018 reply Follow Share In case of Syn counters all the flipflops will get the clocks at the same time, so we need not wait for the previous flipflop to produce the result which means we can run everything in parallel==> one time of flipflop delay. Similarly the combinational circuits doesn't need to wait for any thing ==> one time of combinations ckt delay ===>15+5= 20ns Freq= 1/time=> 50Mhz 0 votes 0 votes radha gogia commented Nov 1, 2018 reply Follow Share When op of one flip flop goes as an input to another flip flop then why don't we consider propogation delay inclusive of all the N flip flops . 0 votes 0 votes Hemanth_13 commented Nov 1, 2018 reply Follow Share All the flipflops will operate at the same time. N-1th flipflops previous state o/p will be the input as current input to nth. So there won't be any delay. All will run in parallel 0 votes 0 votes radha gogia commented Nov 4, 2018 reply Follow Share I have just one doubt , say I have 3 FF ,Now output of 1st flip flop is connected to input of 2nd FF and output of 2nd FF is connected to input of 3rd FF . Now until we get op of 2nd FF , how can we get OP of 3rd FF , so we should take into consideration the delay of all flip flops . 0 votes 0 votes Hemanth_13 commented Nov 4, 2018 reply Follow Share Check this Link https://gateoverflow.in/260633/self-doubt 0 votes 0 votes Please log in or register to add a comment.
1 votes 1 votes Its synchronous counter so , Propagation delap = T(f-f)+ T(combinational) T(pdsyn) = 15 + 5 =20 ns F= 1/T(pdsyn) = 50 HZ shivam001 answered Nov 23, 2019 shivam001 comment Share Follow See 1 comment See all 1 1 comment reply jlimbasiya commented Jan 13, 2020 reply Follow Share So answer will be option A as we require min clock of 20ns . but clock time more than 20ns is allow but less is not allowed 0 votes 0 votes Please log in or register to add a comment.