A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction and 6 clock cycles for DIV instruction respectively.
I0: DIV R2, R0,R1 (The operation is R2←R0/R1)
I1: SUB R2, R5,R2 ( The operation is R2←R5−R2)
I2: MUL R5, R3,R4 (The operation is R5←R3∗R4)
I3: ADD R5, R2,R6 (The operation is R5←R2+R6 )
What is the number of clock cycles needed to execute the above sequence of instructions?
my answer comes 16 cycle
please tell where i did wrong
but answer given is 17 please elaborate with figure