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in CO and Architecture by Loyal (7.1k points) | 141 views
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can you post their solution ?
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@Shaik i am so sorry for such late reply brother.

I get the first part Please see my approach

I need to do square of two 4 bit numbers So size of ROM = 2^4 * 2^4 * 8bit = 256x8 bit

Which can be build easily using 4x16 Decoder ====> 256/16 = 16, 16/16 = 1  Total Decoder = 17

Now i am not getting why and how OR GATES are used ?
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ACE Solution :

 

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By seeing the 3-bit squarer table, you can note down that

D2= 1 for 2 rows (010,110), how you represent this D2, using a 2-i/p OR gate, right?

D3= 1 for 2 rows (011,101), how you represent this D3, using a 2-i/p OR gate, right?

D4= 1 for 3 rows (100,101,111), how you represent this D4, using a 3-i/p OR gate, right?

But note that D1 = 0 always, ===> No need of any OR gate.

D0 = A0 ===> No need of any OR gate.

1 Answer

0 votes
for n-bit squarer

address size=n bit

longest result=2n bit

decoder size=n*2^n

number of OR gate=2n-2

ROM size=2^n*2n

correct option is B
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