1 votes 1 votes CO and Architecture rom digital-logic co-and-architecture decoder + – Na462 asked Nov 7, 2018 Na462 1.0k views answer comment Share Follow See all 4 Comments See all 4 4 Comments reply Shaik Masthan commented Nov 7, 2018 reply Follow Share can you post their solution ? 0 votes 0 votes Na462 commented Nov 14, 2018 reply Follow Share @Shaik i am so sorry for such late reply brother. I get the first part Please see my approach I need to do square of two 4 bit numbers So size of ROM = 2^4 * 2^4 * 8bit = 256x8 bit Which can be build easily using 4x16 Decoder ====> 256/16 = 16, 16/16 = 1 Total Decoder = 17 Now i am not getting why and how OR GATES are used ? 0 votes 0 votes Na462 commented Nov 14, 2018 reply Follow Share ACE Solution : 0 votes 0 votes Shaik Masthan commented Nov 18, 2018 reply Follow Share By seeing the 3-bit squarer table, you can note down that D2= 1 for 2 rows (010,110), how you represent this D2, using a 2-i/p OR gate, right? D3= 1 for 2 rows (011,101), how you represent this D3, using a 2-i/p OR gate, right? D4= 1 for 3 rows (100,101,111), how you represent this D4, using a 3-i/p OR gate, right? But note that D1 = 0 always, ===> No need of any OR gate. D0 = A0 ===> No need of any OR gate. 0 votes 0 votes Please log in or register to add a comment.
0 votes 0 votes for n-bit squarer address size=n bit longest result=2n bit decoder size=n*2^n number of OR gate=2n-2 ROM size=2^n*2n correct option is B altamash answered Jul 8, 2019 altamash comment Share Follow See all 0 reply Please log in or register to add a comment.
0 votes 0 votes LSB of Output is directly connect to LSB of Input. Rest are show in diagram below. ANSWER: B darthJatrJAr answered Jul 11, 2021 darthJatrJAr comment Share Follow See all 0 reply Please log in or register to add a comment.