361 views
0 votes
0 votes

1 Answer

Best answer
1 votes
1 votes
VAS PS PTE PT1 PT2 PT3

32 bits = 232 Bytes

1KB 32 bits = 4B

Number of Entries = 232 / 210 = 222

Table Size = 222 x 22 (PTE) = 224.

Numbers of Entries = 224 / 210 = 214 

 Table Size = 214 x 22 (PTE) = 216.

Numbers of Entries = 216 / 210 = 26

Table Size = 26 x 22 (PTE) = 28

 

Here PT1 and PT2 are completely filled But PT3 is not Completely filled.

Address Spilt  =  

PT3       PT2         PT1    Pages Offset

6 8 8 10

So, the Numbers of Entries in Each of the pages in the Page Table will be 64, 256, 256.

selected by

Related questions

0 votes
0 votes
0 answers
1
superask asked Jan 30, 2017
305 views
0 votes
0 votes
0 answers
2
Gate Fever asked Jan 12, 2019
677 views
consider a system with 48 bit virtual address and page size is 16KB.Operating system uses multilevel paging.page table entry size is 4B.What is the number of entries in t...
0 votes
0 votes
0 answers
3
Gate Fever asked Nov 9, 2018
213 views
0 votes
0 votes
1 answer
4
Gate Fever asked Nov 9, 2018
433 views
I AM GETTING 28%WITH TLB= 140nsWITHOUT TLB= 500nsi havent considered memory access time, just address translation time is cosidered!am i right??