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Consider the following circuit involving a positive edge triggered D FF. Consider the following timing diagram. Let $A_{i}$ represents the logic level on the line a in the i-th clock period. Let $A'$ represent the compliment of $A$. The correct output sequence on $Y$ over the clock periods $1$ through $5$ is:

1. $A_{0} A_{1} A_{1}' A_{3} A_{4}$
2. $A_{0} A_{1} A_{2}' A_{3} A_{4}$
3. $A_{1} A_{2} A_{2}' A_{3} A_{4}$
4. $A_{1} A_{2}' A_{3} A_{4} A_{5}'$

edited | 5.6k views
+14

D=Y= AX + Q'X'

1st clock pulse, X=1, Hence Y=A=A0
2nd clock pulse, x=1, Hence Y=A=A1
3rd clock pulse, x=0, Hence Y=A'=A1'
4th clock pulse, x=1, Hence Y=A=A3
5th clock pulse, x=1, Hence Y=A, A4

$Remark:$ when second clock pulse was applied that time x was showing falling edge, but note that x is not directly connected to the input of D, D will only read the previous value of x (this 2-level circuit made of AND and OR delays X to reach D flip-flop), at the time when clock pulse is getting applied.

0

D = AX + X'Q'

Y = D

Ai represent the logic level on the line A at the i-th clock period. If we see the timing diagram carefully, we can see that during the rising edge, the output Y is determined by the X value just before that rising edge. i.e., during the rising edge say for clk2, X value that determines the output is 1 and not 0 (because it takes some propagation delay for the 0 to reach the flip flop). Similarly, the A output that determines the output for clk i, is Ai-1

For clk1, X is 1, so, D = A = A0

For clk2, X is 1, so D = A = A1

For clk 3, X is 0, so D = Q2' = A1'

For clk4, X is 1, so D = A = A3

For clk5, X is 1, so D = A = A4

by Veteran (425k points)
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0
Sir i understand the sequence of o/p in Y here.. but i don't undesrand when to use A1' or A2' imean to ask i understand the sequence A0 A1 A' A3 and A4 but i m confused about the middle element. please help ..
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it depends on the clock. At 0th clock A0, at 1st clock A1 and so on...............
+3
In clock 2 , X has value 0,why have you taken X=1? @arjun sir
+6
@rahul $X$ value for a clock period $t_i$ is the one just before the start of that clock period -- in the diagram, this corresponds to the value at clock period $t_{i-1}.$
+2
Got it sir.thanks:)
0
positive edge triggered then values of $X$   :    $1,1,0,1,1$ (value just before the clock pulse)

if negative edge triggered then values of $X$:    $1,0,1,1,0$ (value just after the clock pulse)
+35 0

Remark:Remark: when second clock pulse was applied that time x was showing falling edge, but note that x is not directly connected to the input of D, D will only read the previous value of x (this 2-level circuit made of AND and OR delays X to reach D flip-flop), at the time when clock pulse is getting applied

1. Here x is applied to some combinatorial circuit hence considering the delay(AND followed by OR) we take X of previous one.(obvious one)

2. Even if it would have been directly given to D, each circuit has some built in circuit which causes this delay.

@Arjun sir is the second statement true? If we have to deal with such questions with timing diagram.

0

@tusharp

If X would have been directly connected to D -FF

When second clock pulse applied X value will be taken as 0 by FF ..as X will be available to FF when clock applied isn't it ??

0
Thanks for the solution

Explanation: The Flip Flop used here is a Positive edge triggered D Flip Flop, which means that only at the “rising edge of the clock” flip flop will capture the input provided at D and accordingly give the output at Q. And at other times of the clock the output doesn’t change. The output of D flip flop is same as input, i.e. Y=Q=D ( at the rising edge ).

Now, in the question above, 5 clock periods are given, and we have to find the output Q or Y in those clock periods.

First, let’s derive the boolean expression for the Logic gate.

which is :
D = AX + X’ Q’

Now,

In the 1st clock period, (i.e. when t = 0 to 1 )

here the clock has rising edge at t= 0, hence at this moment only, D flip flop will change its state.

In the 1st clock,  X = 1, So,  D = A. Now A logic line may have different levels at different clock periods, i.e. may be high or low, therefore we have to answer with respect to the ith clock period where Ai is the logic level ( high or low ) of logic line A in the ith clock.

So in the 1st clock period, A logic value should be A1 ( i.e. value of A in 1st clock period), but due to the delay provided by the Logic Gates ( Propagation Delay) the value of A used by Flip Flop is previous value of A only, i.e.it will capture the value of D resulted by using the logic line A in the 0th clock period, which is A0. Same happens with the value of X, i.e. instead of Xi, previous value of X  is used in the in the ith clock period, which is Xi-1.

Now, In the 1st clock period value of X is same as in the 0th clock, i.e. logic 1. So, X = 1 ,and A = A0, therefore, D = A0, and hence Q = Y = A0

Similarly we have to do for other clock periods, i.e. instead of taking Ai and Xi,  Ai-1 and Xi-1 need to be taken for getting the output in the ith clock period.

In the 2nd clock period, (i.e. when t = 1 to 2 )

X = 1 ( value in the previous clock), So, D = A1 ( value of A in the previous clock)  , therefore Q = Y = A1

In the 3rd clock period, (i.e. when t = 2 to 3 )

X = 0 ( value in the previous clock,see the timing diagram), So, D = Q’ = A1′ , therefore Q = Y = A1′   ( because of the feedback line )

In the 4th clock period, (i.e. when t = 3 to 4 )

X = 1 ( value in the previous clock,  ), So, D = A3 , therefore Q =  Y = A3

In the 5th clock period, (i.e. when t = 4 to 5 )

X = 1 ( value in the previous clock ), so, D = A4 , therefore Q = Y = A4

Hence the output sequence is : A0 A1 A1′ A3 A4

by Active (4.7k points)
0
In 3rd clock pulse it should be a2 complement why it is a1 complement
0
how do we know when to and when not to consider the delays.The value of A is understandable, but why are we using value X with respect to previous clock cycle?
0
From the timing diagram  we can get such idea ..
0
We start counting from clock 0 to clock 1.. X is 1.. clock 1 to clock 2 , X is 0 in timing diagram , why do we chose X as 1 ??
+3
Just see the circuit diagram , during the rising edge for clock2, X value that determines the output is 1 and not 0 (because it takes some propagation delay for the 0 to reach the flip flop) .
0
Ok, thank you sir .
+1 vote

I think answer may be B

if see the cases

D=AX+X'Q'

Y=D

 A X Q Q' y 0 1 0 1 0=A 0 1 1 0 0=A 1 1 0 1 1=A 1 1 1 0 1=A A 0 A A' A' A 1 A' A A A 1 A A' A
by (219 points)