GATE1991-5-c

Question

Find the maximum clock frequency at which the counter in the figure below can be operated. Assume that the propagation delay through each flip flop and each AND gate is $10$ $\text{ns}$. Also assume that the setup time for the $JK$ inputs of the flip flops is negligible.

Comments

What I know is Total time (Propagation) = T(flip flop) + T(combinational circuit)

So from the above Total time= 10(Flip Flop) + 30(combinational AND gate);

f=1/T and we can solve easily . But here why only one AND gate delay is considered ?

Expalin plz.

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@bikram sir

Answer not should be 30(3 And Gate ) + 10 ( Synch Circuit) = 40 ns

1/40 ns= 25 Mhz ?

Why here they have taken it only for 1 And and 1 FF ?

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This might be silly but I can't see any combinational circuit such that output of flip flops is again given to input of flip flops. plz help.

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Can You check K1, K2?

Answer 1

In a JK flip flop the output toggles when both J and K inputs are $1.$ So, we must ensure that with each clock the output from the previous stage reaches the current stage.

Setup time is defined as the minimum amount of time before the clock's active edge that the data must be stable for it to be latched correctly

It is given that set up time is negligible - means as soon as data is stable, next clock can be given. 

Time to get output from $FF$ once input (and clock) is given  = $10ns.$ (Propagation Delay)

Time for inputs to reach $FF_1 = 0.$ (Zero AND gate)

Time for inputs to reach $FF_2 = 10.$ (One AND gate)

Time for inputs to reach $FF_3 = 20.$ (Two AND gates)

So, minimum time period needed for clock is $10 + \max(0,10,20) = 10 + 20 = 30ns$ which would mean a maximum clock frequency of $1/30 GHz = 33.33 MHz$

Comments

Is the clock frequency only dependent on no. of AND gates and not on no. of flip flops? Why can't we take no. of flip flops as the the multiple for propagation delay?

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We just have to ensure the output from a previous flipflop reaches the next flipflop (A flipflop can store a bit) within the time period of the operating clock. So, we just need to consider the stages between these. In the question there is only one AND gate in this stage. If there were 2, we should have multiplied the propagation delay by 2.

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sir , if just ensure that o/p of previous one reaches to next flip flop then ... for last flip flop , we have to consider 2nd flip flop delay also ...??

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yes, for FF 3, we consider delay of FF 2 and the AND gate delay.

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then why only 20 ns .. is it 30ns .. 2 and gate for ff2 and ff3 , and i ff2 before ff3 ??

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we are only considering the time from input of FF 2 to input to FF 3.

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sorry sir , i am not getting... :(

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When a clock comes it activates all the FFs simultaneously. So, we want to ensure the output of one stage reaches the input of next before the next clock. So, between two clocks, input must produce output and this output should reach next FF.

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yes , but why only we are considering FF 2 TO FF3, not FF1 to FF2 ... Here i am confuse  ..

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thats the same delay rt?

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suppose the circuit was not the same, we should have considered all these stages, and taken the maximum time period (min. frequency).

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okkk.... they have same delay ... and as clock given at same time so ..that delay consider only once ....

sorry .. i am considering for each ...thank you :)

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http://electronics.stackexchange.com/questions/208576/find-maximum-clock-frequency-at-which-a-given-counter-can-be-operated?noredirect=1#comment441169_208576

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it should be 1/30 as...after 20 3rd jk has it's inputs & it takes another 10 to produce the output....so 30

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In a synchronous counter, at the end of a clock cycle the output should be present at each point that will further be used as a input to flip flops. Am i right ?

And if input for flip flops is present before giving clock. Then definitely $T_delay = 20ns$

Otherwise if input of AND gates depends on other AND gate, then $T = 10 +(10+10+10) = 40ns$

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what would have happened in asynchronous counter??

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@Arjun Sir,

Is this Right ? https://gateoverflow.in/86195/me-test

This is the same related question.

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@Arjun Sir

Thanks !!

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@sushmita in asynchronous case there is no clock rt?

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arjun sir clock is there in asynchronous according to me.

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yes, it is there to the first FF. The maximum clock frquency won't be more than 50 MHz in that case also, but might be even lower. Have to see Morris Mano to tell more..

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sir what i know is that the clock time is equal to the delay of all flipflops and combinational circuit in aynchronous counter. Its not right??

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SRC: https://www.doc.ic.ac.uk/~nd/surprise_96/journal/vol4/cwl3/report.html#design

In the series carry scheme, the time to propagate the change in Q0 must take into account the propagation delays of the 3 AND gates (A, B, C)

so it is T+A+B+C here rt??

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Arjun sir, in asynchronous counter I think we should consider the delay of all the flip-flops because the output of one flip-flop serves as the input to the next one. So I think delay should be 30ns for 3 ff and 20 n's for intermediate and gates. Plz plz check.

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how can you say that it is asynchronous clock ? same clock is attached to

all flip flops here , so it should be synchronous.plz correct me.

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But in question https://gateoverflow.in/86195/me-test , the delay for each and gate is considered.Whats the difference?

The input to 3rd flip flop is depending is two and gate delays as per this link

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what if JK was not on high and given different inputs like 01 or 10 then ??

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thank u arjun sir.....

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https://gateoverflow.in/229112/confusion-in-synchronus-series-counter

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Refer: https://electronics.stackexchange.com/questions/328294/maximum-frequency-of-the-synchronous-counter

ignoring the carry output of the circuit (the third AND gate). The question is only about the maximum clock frequency of the counter itself. If that output needs to be valid, then the clock period will have to be even longer.

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@Arjun Sir , how the time for input to reach the second FF is 10ns, it should be 20ns, i.e propragation time of first FF and the AND gate , please explain

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What if propagation delay for each flip flop was different? Let's say 1ns, 2ns, 3ns.

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Will not the final output from ff3 have 1 AND  gate more delay before we use it finally. If yes then

 

minimum time period needed for the clock is 

10+max(0,10,20,30) =>  10+30= 40 ns which would mean a maximum clock frequency of 1/40ns 

= 25 MHz

 

Please correct if thinking wrong. Thank you.

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My doubts,

Pd of FFs are 10ns. clock is simultaneously given in each FF.

J0K0 inputs are given,so when cock is active we can get this immediately,but to get the inputs of J1K1 we've to spend 20ns( 10ns for FF & 10ns for OR gate).

likewise to get the inputs at J2K2 we've to spend more 20ns(10ns for FF & 10ns for OR)

so we'll get o/p at Q2 at the time of 20 + 20 = 40ns.

again if I consider the last OR gate, then finally the total time is 50ns.

Don't know where I'm lagging.

Seniors please help.

see I'm taking this in the ay like - for J1K1 & J2K2 FF can't operate untill it gets the output from it's previous AND gate which is total 20ns.

anyone please clear this confusion.

 

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https://gateoverflow.in/26442/gate1991-5-c?show=314#c314

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https://gateoverflow.in/229112/confusion-in-synchronus-series-counter

https://electronics.stackexchange.com/questions/328294/maximum-frequency-of-the-synchronous-counter

Answer 2

A clock cycle time should be large enough that all flip-flops can come in to a stable state before the next clock cycle starts
(or) from the time we provide the input and till the moment output is available will be a cycle.
Suppose cycle 1 is just completed and cycle 2 is just about to start:
1. to reach the result of q0Λ1 to J1K1 it needs $10 ns$
2. to reach the result of (q0Λ1)ΛQ1 to J2K2, other 10 nanoseconds are needed.
3. Now, we need other 10  nanoseconds to operate flipflops as the propagation delay of each flip flop is 10ns.
4. Finally, we need 10 more nanoseconds to get the output from the last AND gate.

For better understanding we can enclose this circuit in a box with one input-pin and one output-pin out, when we provide input to the box, we need at least 40ns to get the output.

Answer should be (1/(2*10ns + 10ns + 10ns) = $\frac{1}{40ns} = 25MHZ$.

Comments

I took think it should be 40ns.

By the time of next clock pulse. All current changes should be settled.

https://electronics.stackexchange.com/questions/328294/maximum-frequency-of-the-synchronous-counter

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@rahul that's what i said, right?

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Yes.I was trying to say that this answer seems to be correct than the selected one

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Each FF along with the AND gate is an independent module since the clock is given synchronously to each FF.  Each module takes 20ns to produce next output. So the output is available after every 20ns. So cycle time is 20ns and thus freq. is 50MHz

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@Manu Thakur Why clock is required for last Nand Gate, it can work even without clock pulse being active

Answer 3

So at all I have concluded , it had asked maximum clock frequency .

And as freq=1/Time period

So we will take best case .

As it is synchronous circuit than all flip flop activate simultaneously and here key is

"Maximum clock frequency at which the counter in the figure below can be operated."

So 1FF+1AND GATE =20 NS

1/20=50 MHZ.

Answer 4

As all flip flop are connected to common clock so it is Synchronous Counter
all flip flop changes simultaneously
and there are 3 AND gates
For last FF input will be avail after 2(AND gate)*10

So Frequency = $\frac{1}{t_{ff} + 2t_{and}}$
                    = $\frac{1}{10 + 20}$
                    = 0.033 = 33.33MHz

Comments

yes . this is according to the formula. right . one confusion. i think 20 second time period will be enough. if all will get the time of 20 why the output will not be generated. ??

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https://gateoverflow.in//207/gate1991-05-c?show=207#viewbutton

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The answer would be 1/20 because 2nd AND GATE do not have to wait for getting the output of first AND GATTE.

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why ? it will depend .

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@bikram sir please describe the answer ....