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53 votes
53 votes

Find the maximum clock frequency at which the counter in the figure below can be operated. Assume that the propagation delay through each flip flop and each AND gate is $10\;\text{ns}$. Also, assume that the setup time for the $JK$ inputs of the flip flops is negligible.

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5 Answers

Best answer
101 votes
101 votes

In a $\text{JK}$ flip flop the output toggles when both $\text{J}$ and $\text{K}$ inputs are $1.$ So, we must ensure that with each clock the output from the previous stage reaches the current stage.

Setup time is defined as the minimum amount of time before the clock's active edge that the data must be stable for it to be latched correctly

It is given that setup time is negligible - means as soon as data is stable, the next clock can be given. 

  • Time to get output from $FF$ once input (and clock) is given  $= 10ns.$ (Propagation Delay)
  • Time for inputs to reach $FF_1 = 0.$ (Zero AND gate)
  • Time for inputs to reach $FF_2 = 10.$ (One AND gate)
  • Time for inputs to reach $FF_3 = 20.$ (Two AND gates)

So, minimum time period needed for clock is $10 + \max(0,10,20) = 10 + 20 = 30ns$ which would mean a maximum clock frequency of $1/30 GHz = 33.33 MHz$

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20 votes
20 votes

A clock cycle time should be large enough that all flip-flops can come in to a stable state before the next clock cycle starts
(or) from the time we provide the input and till the moment output is available will be a cycle.
Suppose cycle 1 is just completed and cycle 2 is just about to start:
1. to reach the result of q0Λ1 to J1K1 it needs $10 ns$
2. to reach the result of (q0Λ1)ΛQ1 to J2K2, other 10 nanoseconds are needed.
3. Now, we need other 10  nanoseconds to operate flipflops as the propagation delay of each flip flop is 10ns.
4. Finally, we need 10 more nanoseconds to get the output from the last AND gate.

For better understanding we can enclose this circuit in a box with one input-pin and one output-pin out, when we provide input to the box, we need at least 40ns to get the output.

Answer should be (1/(2*10ns + 10ns + 10ns) = $\frac{1}{40ns} = 25MHZ$.

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8 votes
8 votes
As all flip flop are connected to common clock so it is Synchronous Counter
all flip flop changes simultaneously
and there are 3 AND gates
For last FF input will be avail after 2(AND gate)*10

So Frequency = $\frac{1}{t_{ff} + 2t_{and}}$
                    = $\frac{1}{10 + 20}$
                    = 0.033 = 33.33MHz
edited by
8 votes
8 votes
So at all I have concluded , it had asked maximum clock frequency .

And as freq=1/Time period

So we will take best case .

As it is synchronous circuit than all flip flop activate simultaneously and here key is

"Maximum clock frequency at which the counter in the figure below can be operated."

So 1FF+1AND GATE =20 NS

1/20=50 MHZ.
Answer:

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