14 votes 14 votes Implement a circuit having the following output expression using an inverter and a nand gate $$Z=\overline{A} + \overline{B} +C$$ Digital Logic gate1995 digital-logic k-map normal descriptive + – Kathleen asked Oct 8, 2014 • recategorized Apr 25, 2021 by Lakshman Bhaiya Kathleen 2.6k views answer comment Share Follow See 1 comment See all 1 1 comment reply Shashwat21225 commented Dec 30, 2019 reply Follow Share For part b, click below-- https://gateoverflow.in/203837/gate1995-15-b?show=203837#q203837 0 votes 0 votes Please log in or register to add a comment.
Best answer 19 votes 19 votes The circuit can be implemented as follows: LeenSharma answered Jul 6, 2016 • edited May 19, 2019 by ajaysoni1924 LeenSharma comment Share Follow See all 4 Comments See all 4 4 Comments reply anchitjindal07 commented Dec 19, 2018 reply Follow Share How to do it with NAND gates with 2 inputs 0 votes 0 votes Srinivas_Reddy_Kotla commented Jul 16, 2019 reply Follow Share https://gateoverflow.in/?qa=blob&qa_blobid=3871474690955860319 4 votes 4 votes Srinivas_Reddy_Kotla commented Jul 16, 2019 reply Follow Share See the image provided in the link.... Correct me if there is any minimal way to do the same 0 votes 0 votes toxicdesire commented Sep 17, 2019 reply Follow Share Is it a requirement in the question that only one NAND gate should be used? It does say in the question "an inverter and a NAND gate", and both answers here use 3-input NAND, that's why I'm asking. 0 votes 0 votes Please log in or register to add a comment.
1 votes 1 votes So in this way, we can make $NAND$ gate of the expression Rishi yadav answered Dec 9, 2018 Rishi yadav comment Share Follow See 1 comment See all 1 1 comment reply deCiFer598 commented Oct 2, 2020 reply Follow Share In the first two diagrams the AND gates should be OR gates 0 votes 0 votes Please log in or register to add a comment.