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Given a non-pipelined architecture running at 1GHz, that takes 5 cycles to finish an instruction. You want to make it pipelined with 5 stages. The increase in hardware forces you to run the machine at 800MHz. The only stalls are caused by memory and branch instructions. 25% of the total instructions are memory instructions and a stall of 70 cycles happens in 2% of the memory instructions. 20% of the total instructions are branch instructions and a stall of 2 cycles happens in 10% of the branch instructions. What is the speedup that can be achieved with pipelining as compared to non-pipelined design?
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