Digital Logic: GATE-ECE-2016

Question

answer is 6
but I’m getting 5(delay of NOR gate+delay of 1st MUX+delay of 2nd MUX)=2+1.5+1.5=5 ns
where is extra 1 ns delay coming from?

Comments

When T=0

one NOR gate + 1MUX + 1 MUX=> 2+1.5+1.5==>5

When T=1

One inverter + One MUX + NOR + Another MUX = 1 + 1.5 + 2 + 1.5 ===>6

Note that inverter @ select lines is done at parallel.

Hope this helps

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it is MUX and note that the selecting lines are inverse to each other

case 1 :-    T=0 ===> i0 of Mux1 and i1 of Mux2 need to evaluate.

               at time k=0, P,Q,R,S and T are loaded ===> i0 of Mux1 available at k=2 (due to NOR gate) then MUX1 evaluate completes at k=2+1.5 = 3.5, output of MUX1 is used as i1 of Mux2 ===> at k=3.5+1.5(for MUX2 evaluation) = 5, MUX2 evaluation completes.

case 2 :-    T=1 ===> i1 of Mux1 and i0 of Mux2 need to evaluate.

               at time k=0, P,Q,R,S and T are loaded ===> i1 of Mux1 available at k=1 (due to NOT gate) then MUX1 evaluate completes at k=1+1.5 = 2.5, output of MUX1 is used as i0 of Mux2 ===> at k=2.5+2(for evaluating i0 of MUX2 due to NOR gate ) = 4.5, Now MUX2 evaluation completes at 4.5 + 1.5(for evaluating MUX2 ) = 6

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why at any given time only one nor gate is active ?