doubt gfg test

Question

Comments

Y will zero on every clock pluse??

---

can you explain bhai

---

The output of  D flipflop is same as its input

For the second flipflop input will never be one because you are giving  x and x' as input to AND gate so the output will be x.x' => 0 which is input to second flipflop so it will give 0 as o/p

Edit : 

Sorry didn't observe intial values of the flip-flop 1 as it is 0 Q' will be 1 => just for one clock pluse the o/p will get high signal after one clock pulse it will said as above.

Thanks @Shaik Masthan

---

@Hemanth_13

check, there is setup time... Moreover it is a gate question, search in previous papers