Effective address time for a cache comprising of L1 and L2 cache =9ns
hit ratio of L1 cache = 0.8
hit ratio of L2 cache = 0.9
memory access time =100ns
Miss penalty of L1 cache = 25ns
Access times for L1 and L2 caches are x and y ns;
let z=x+y; what’s z??
I am getting 20.33 but the given answer is different!