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in CO and Architecture by (189 points) | 35 views
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Option b
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How?
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Design 1 is direct cache with 8 lines so

K mod 8=I

0mod 8=0 (miss)

3 mod 8=3 (miss)

14 mod 8=6 (miss)

11 mod 8=3 (miss)

4mod 8 =4 (miss)

11 (hit)

8mod 8=0(miss)

0mod8=0 (miss)

 

Miss penalty=8 cycles

Total miss=7

So total cache miss penalties =8*7=56
+1
Design 2 is set associative cache

No of sets=8/2=4

I.e. 4 sets with 2 lines each set

 

I=K Mod 4

0mod 4=0 (miss)

3mod 4=3 (miss)

14 mod4 =2 (miss)

11 mod  4=3 (miss)

4mod 4=0 (miss)

11mod 4=3 (hit)

8mod 4=0(miss)

0 mod 4=0 (miss)

Total miss=7

Penalty on each miss=10 cycles

Total cache miss penalty =10*7=70 cycles

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