0 votes 0 votes CO and Architecture co-and-architecture cache-memory made-easy-booklet + – Gaurangi Katiyar asked Dec 2, 2018 • retagged Aug 1, 2022 by Shubham Sharma 2 Gaurangi Katiyar 282 views answer comment Share Follow See all 4 Comments See all 4 4 Comments reply Priyanka Agarwal commented Dec 2, 2018 reply Follow Share Option b 0 votes 0 votes Gaurangi Katiyar commented Dec 2, 2018 reply Follow Share How? 0 votes 0 votes Priyanka Agarwal commented Dec 2, 2018 reply Follow Share Design 1 is direct cache with 8 lines so K mod 8=I 0mod 8=0 (miss) 3 mod 8=3 (miss) 14 mod 8=6 (miss) 11 mod 8=3 (miss) 4mod 8 =4 (miss) 11 (hit) 8mod 8=0(miss) 0mod8=0 (miss) Miss penalty=8 cycles Total miss=7 So total cache miss penalties =8*7=56 1 votes 1 votes Priyanka Agarwal commented Dec 2, 2018 reply Follow Share Design 2 is set associative cache No of sets=8/2=4 I.e. 4 sets with 2 lines each set I=K Mod 4 0mod 4=0 (miss) 3mod 4=3 (miss) 14 mod4 =2 (miss) 11 mod 4=3 (miss) 4mod 4=0 (miss) 11mod 4=3 (hit) 8mod 4=0(miss) 0 mod 4=0 (miss) Total miss=7 Penalty on each miss=10 cycles Total cache miss penalty =10*7=70 cycles 1 votes 1 votes Please log in or register to add a comment.