Question

The ALU, the bus and all the register are identical in size. The instruction "memory write" has the register transfer interpretation M[(R1)] ← R2. The minimum number of clock cycles needed for execution cycle of this instruction if memory write completion takes 1 cycle is

a) 2              b)3

c)4               d)5

Answer 1

It can be done in 3 cycles

1.R2out,MDRin

2.R1out,MARin

3.MARout,MDRout,WRITE(this write can be done in this cycle only)

Ref: https://en.wikipedia.org/wiki/Datapath

Comments

Any reference?

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https://en.wikipedia.org/wiki/Datapath