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Consider a non-pipelined processor design which has a cycle time of 10ns and average CPI of 1.6. If each pipeline stage adds extra 20ps due to register setup delay. The pipeline stalls 25% of the time for 1 cycle and 10% of the time for 2 cycles (these occurrences are disjoint). What is the new CPI ?(ans=2.05)

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Let's assume there are 100 instructions.

Total number of clock cycles required =

100*1.6 = 160 (Un-pipeline CPI)

25 * 1  = 25 (25% take 1 stall)

10 * 2 = 20 (10% take 2 stall)

Total clock cycle = 160 + 25 + 20 = 205

New CPI = 205/100

=2.05

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