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BASIC CAPACITY= $1K*8$

TARGET CAPACITY= $32K*8$

#CHIPS REQUIRED= TARGET/GIVEN

$\Rightarrow\frac{ 32K*8}{1K*8}$$\Rightarrow32$

$\Rightarrow 2^{5}$

$\Rightarrow \log {_{2}} {2^5}$

therefore 5 DECODERS are required.

HENCE OPTION B

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→ The capacity of the RAM needed = 16K
→ Capacity of the chips available = 1K
→ No. of address lines = 16K/1K = 16
→ Hence we can use 4×16 decoder for this. But we were only given 2×4 decoders.
→ So, 4 decoders are required in inner level as from one 2×4 decoder we have only 4 output lines whereas we need 16 output lines.
→ To point to these 4 decoders, another 2×4 decoder is required in the outer level.
→ Hence no. of 2×4 decoders to realize the above implementation of RAM = 1+4 = 5
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✌ Edit necessary (_Shubham_.Singh_ “Required capacity is 32K”)
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