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A logic network has two data inputs $A$ and $B$, and two control inputs $C_0$ and $C_1$. It implements the function $F$ according to the following table.
$${\begin{array}{|cc|c|}\hline \textbf{C_1}& \textbf{C_0}& \textbf{F}\\\hline 0&0&\text{\overline{A + B}} \\ 0&1& \text{A + B} \\ 1&0& \text{A \oplus B } \\ \hline \end{array}}$$Implement the circuit using one $4$ to $1$ Multiplexer, one $2-$input Exclusive OR gate, one $2-$input AND gate, one $2-$input OR gate and one Inverter. This is the implementation asked in question

• $C_0 = 0 , C_1 = 0$  line $00$ will be selected and $F$ will give $(A+B)'$
• $C_0 = 0 , C_1 = 1$  line $01$ will be selected and $F$ will give $(A\oplus B)$
• $C_0 = 1 , C_1 = 0$  line $10$ will be selected and $F$ will give $(A+B)$
• $C_0 = 1 , C_1 = 1$ line $11$ will be selected and $F$ will give $(A+B)'.(A+B) =0$

edited
@Praveen Saini sir can we have enable input $\bar{EN}$ for MUX ? in that case, when both the select lines are 1, can we design it like it'll disable the MUX giving input 1 to $\bar{EN}$ using the AND gate ? for rest of  the valid selector inputs, it'll be enabled since we use AND.
Yes, you are right. we can disable the MUX at 1,1 at select lines
Sir no combination for C0 = 1 and C1 = 1 given ..why you have taken (A+B).(A+B)'

Why can't we just set I4 to 0 externally instead of using X.X' ??
For the values c0=1, c1=1, why is F taken as 0?

DOUBT: why input is taken as (A+B)’.(A+B)  for c0=1,c1=1?

just to make zero?

CORRECTION:in the question output is EXOR  for c0=1,c1=0 ? if  wrong then pls explain?

edited

In question "using one 2 input AND gate" is mention, so for that purpose (A+B)(A+B)’

is used.

@Pranavpurkar

for the correction part
no there is no problem in solution in the question the sequence is C1 then C0
and in solution the sequence is C0 then C1

@JAINchiNMay

why C1 is not taken as MSB ?

you can take C1 also as MSB you have to interchange the input of MUX accordingly

@JAINchiNMay Thanks :)