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A logic network has two data inputs $A$ and $B$, and two control inputs $C_0$ and $C_1$. It implements the function $F$ according to the following table.
$${\begin{array}{|cc|c|}\hline \textbf{C_1}& \textbf{C_0}& \textbf{F}\\\hline 0&0&\text{\overline{A + B}} \\ 0&1& \text{A + B} \\ 1&0& \text{A \oplus B } \\ \hline \end{array}}$$Implement the circuit using one $4$ to $1$ Multiplexer, one $2-$input Exclusive OR gate, one $2-$input AND gate, one $2-$input OR gate and one Inverter.

This is the implementation asked in question

• $C_0 = 0 , C_1 = 0$  line $00$ will be selected and $F$ will give $(A+B)'$
• $C_0 = 0 , C_1 = 1$  line $01$ will be selected and $F$ will give $(A\oplus B)$
• $C_0 = 1 , C_1 = 0$  line $10$ will be selected and $F$ will give $(A+B)$
• $C_0 = 1 , C_1 = 1$ line $11$ will be selected and $F$ will give $(A+B)'.(A+B) =0$

@JAINchiNMay

why C1 is not taken as MSB ?

you can take C1 also as MSB you have to interchange the input of MUX accordingly

@JAINchiNMay Thanks :)