in CO and Architecture retagged by
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in CO and Architecture retagged by
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I think it should be 33.33
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shouldn't it be 50mhz,

1 2 3 4 5 6 7 8 9 10 11 12
IF ID OF EX EX WB            
  IF ID OF   EX EX WB        
    IF ID   OF   EX EX WB    
      IF   ID   OF   EX EX WB

Hence each instruction will take 2 clock cycles to finish.

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Yes you are right, its mistake from my side it should be 50MHz as we will have to extra cycles and one cycle takes 10ns => 20 ns for one instruction ==> Freq = 1/20 ==> 50MHz
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answer will be 25 MHz.

credit:@aambazinga

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Yes brother that will be stall.
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@prateek bro i got the explanation that why it is happening,tell me one more thing ,you said that after instruction decode while fecthing the oprerand then only get to know that it is depending on previous thats why  OF stage have to wait untill operand not available , and thats's why ,you introduced 3 stall  in 4, 5 ,6 clock cycle, and similarly for I3 there will be dependency so you introduced 6 stall 5 to 10 clock cycle 

i want to ask can our circuitry detect the dependency in ID statge itself ?

if it will detect in ID stage then also stall would be same and we would do OF after WB 

please clear my it and if a said anything wrong then correct me
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 untill operand not updated we can't fetch the operand simply ,when $I_0$ completed its updation then only $I_1$ can fetch it.dependency will detect in ID stage ,ID stage simply decode the instruction like how many byte of instruction ,which type of addressing mode operands are using etc  

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