0 votes 0 votes CO and Architecture zeal co-and-architecture instruction-execution zeal2018 + – Prince Sindhiya asked Dec 8, 2018 retagged Mar 6, 2019 by ajaysoni1924 Prince Sindhiya 1.1k views answer comment Share Follow See all 11 Comments See all 11 11 Comments reply Show 8 previous comments Hemanth_13 commented Dec 9, 2018 reply Follow Share I think it should be 33.33 0 votes 0 votes Shivam Kasat commented Dec 9, 2018 reply Follow Share shouldn't it be 50mhz, 1 2 3 4 5 6 7 8 9 10 11 12 IF ID OF EX EX WB IF ID OF EX EX WB IF ID OF EX EX WB IF ID OF EX EX WB Hence each instruction will take 2 clock cycles to finish. 0 votes 0 votes Hemanth_13 commented Dec 9, 2018 reply Follow Share Yes you are right, its mistake from my side it should be 50MHz as we will have to extra cycles and one cycle takes 10ns => 20 ns for one instruction ==> Freq = 1/20 ==> 50MHz 1 votes 1 votes Please log in or register to add a comment.
0 votes 0 votes answer will be 25 MHz. credit:@aambazinga Prateek Raghuvanshi answered Dec 9, 2018 edited Dec 9, 2018 by Prateek Raghuvanshi Prateek Raghuvanshi comment Share Follow See all 6 Comments See all 6 6 Comments reply Hemanth_13 commented Dec 9, 2018 reply Follow Share Brother..why two clock cycles for OF stage ?Although it doesn't make any difference. And in general we use operator forwarding right though it wasn't specified. 0 votes 0 votes Prateek Raghuvanshi commented Dec 9, 2018 reply Follow Share Brother ,after instruction decode while fecthing the oprerand then only get to know that it is depending on previous thats why OF stage have to wait untill operand not available. 0 votes 0 votes Hemanth_13 commented Dec 9, 2018 reply Follow Share Your are right but for I1 first OF should be a stall right ? i.e. during 3rd clk of I1 0 votes 0 votes Prateek Raghuvanshi commented Dec 9, 2018 reply Follow Share Yes brother that will be stall. 0 votes 0 votes Prince Sindhiya commented Dec 10, 2018 reply Follow Share @prateek bro i got the explanation that why it is happening,tell me one more thing ,you said that after instruction decode while fecthing the oprerand then only get to know that it is depending on previous thats why OF stage have to wait untill operand not available , and thats's why ,you introduced 3 stall in 4, 5 ,6 clock cycle, and similarly for I3 there will be dependency so you introduced 6 stall 5 to 10 clock cycle i want to ask can our circuitry detect the dependency in ID statge itself ? if it will detect in ID stage then also stall would be same and we would do OF after WB please clear my it and if a said anything wrong then correct me 0 votes 0 votes Prateek Raghuvanshi commented Dec 10, 2018 reply Follow Share @ Prince Sindhiya untill operand not updated we can't fetch the operand simply ,when $I_0$ completed its updation then only $I_1$ can fetch it.dependency will detect in ID stage ,ID stage simply decode the instruction like how many byte of instruction ,which type of addressing mode operands are using etc 0 votes 0 votes Please log in or register to add a comment.