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Consider a device with 1MB per second transfer rate and operating in cycle stealing mode of DMA. It requires 0.5 microsecond to transfer the data (1 byte) when it is ready or prepared. Percentage of CPU blocked due to DMA?
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So brother 50 percent is the correct answer?

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https://gateoverflow.in/250088/cycle-stealing-dma-doubt

see this.

in DMA case we check for interrupts at the end of every pipeline operation whereas for  other interrupts only check at the end of each instructions.

pipelining has nothing to do with this question i suppose

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but this question is based on cycle stealing
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Device transfer is given as 1 MBPS  which means 1 MB per sec, So 1B is transferred in 1 microsec, Transfer Time is given as 0.5 microsec, So (0.5/1+0.5) x 100 % = 33.33%

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