0 votes 0 votes Consider a device with 1MB per second transfer rate and operating in cycle stealing mode of DMA. It requires 0.5 microsecond to transfer the data (1 byte) when it is ready or prepared. Percentage of CPU blocked due to DMA? CO and Architecture co-and-architecture dma + – Ajit J asked Dec 9, 2018 retagged Jul 30, 2022 by Shubham Sharma 2 Ajit J 1.2k views answer comment Share Follow See all 10 Comments See all 10 10 Comments reply Show 7 previous comments Ajit J commented Dec 9, 2018 reply Follow Share So aambazinga brother 50 percent is the correct answer? 0 votes 0 votes Satbir commented Dec 9, 2018 reply Follow Share https://gateoverflow.in/250088/cycle-stealing-dma-doubt see this. in DMA case we check for interrupts at the end of every pipeline operation whereas for other interrupts only check at the end of each instructions. pipelining has nothing to do with this question i suppose 0 votes 0 votes Ajit J commented Dec 9, 2018 reply Follow Share but this question is based on cycle stealing 0 votes 0 votes Please log in or register to add a comment.
0 votes 0 votes Device transfer is given as 1 MBPS which means 1 MB per sec, So 1B is transferred in 1 microsec, Transfer Time is given as 0.5 microsec, So (0.5/1+0.5) x 100 % = 33.33% sakshipandey.exe answered Sep 21, 2022 sakshipandey.exe comment Share Follow See all 0 reply Please log in or register to add a comment.