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Consider a 2-level L1 and L2 memory hierarchy system. The associativity of L1 towards processor is more. L1 (cache) has accessing time of 15 ns and L2 (main memory) has an accessing time of 100 ns. Writing takes 30 ns for L1 and 150 ns for L 2. Assume 30% of the time L1 misses the instruction. Half of the instruction are read only instructions. What is the average access time for the system if it uses write through protocol?
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